1. Field of the Invention
The present invention relates to a ball grid array type semiconductor device comprising a flexible tape carrier, more particularly, to a multipin semiconductor device having a narrow-pitched through hole connection structure.
2. Description of the Related Art
A ball grid array type semiconductor device comprising a flexible tape carrier is proposed in Japanese Patent Laid-open No. 7-321157 as an example. This discloses a micro semiconductor package, in which the size of a chip is nearly equal to that of a package.
As a fourth embodiment of this proposal discloses a structure, in which a metal-filled through hole is used as a connection between an internal electrode of a chip and an inner lead (see FIG. 5). Exemplary dimensions are as follows. For internal electrodes arranged in a single row at 100-.mu.m pitch, a through hole of 50 .mu.m in diameter and an inner lead of 70 .mu.m in width are illustrated. A method for processing through holes, in which a carbonic acid gas, a YAG laser and an excimer laser is used, is disclosed.
In a seventh embodiment, the proposal also entions a limit to the number of outer electrodes which can be arranged in a portion, on which a bare chip is mounted, as shown in FIG. 5. As described in the embodiment, when external electrodes are arranged at a pitch of 0.5 mm, an external electrode mount area is 7 mm square, and the number of pins is 226 or more, pads cannot be formed in the mount area, so that the pads need to be arranged in a fan-out. Conversely, unlike a method such as a conventional TAB (Tape Automated Bonding), external electrodes can be also disposed on the portion on which a bare chip is mounted, resulting in improved area efficiency.
On the other hand, as the performance of semiconductor device is improved, a semiconductor package needs to be miniaturized and to have a multipin structure. Under such conditions, it is proposed that inner electrodes have a pitch of 40 .mu.m or less and the number of outer electrodes is 500 pins or more.
Therefore, it appears that a semiconductor device having good area efficiencies, in which internal electrodes of a chip have a pitch of 40 .mu.m or less, can be provided by employing the method disclosed in the Japanese Patent Laid-open No. 7-321157. However, the above mentioned method has a problem that it is difficult to connect internal electrodes at a narrow pitch of 40 .mu.m.
The width of an internal lead at a connection between an inner lead and an internal electrode of a chip is determined by taking into account the diameter of a through hole and the clearances on the opposite sides thereof when a through hole is formed by means of laser or plating. However, actually, the smallest possible diameter of a hole formed by means of laser is about 25 .mu.m and allowable diviation in the alignment of holes is 5-10 .mu.m, and an hence the width of the inner lead becomes 35-45 .mu.m, so that the width d of a gap between adjoining inner leads becomes about 0 as illustrated in FIG. 3, which may cause a short circuit.
As a wiring method, in which a short circuit can be avoided, an arrangement in which through hole portions of the inner leads are staggered, is also provided. However, in this case, as shown in FIG. 3, if two adjacent wires are arranged in the same direction, a short may occur. And when the adjacent wires are arranged in the opposite directions on staggered patterns, the number of wires which can be led onto the bare chip mounting area and the number of wires which can be led into a region outside the bare chip each are half or less the total number of internal electrodes of a chip. For example, when the area of the bare chip mounting portion has no room, and even if an attempt is made to lead more wires into the region outside the bare chip, it is impossible to lead the wires from a half or more of the total number of internal electrodes, as can be seen from FIG. 1.